Cache Miss
A `cache miss` occurs when a processor, storage controller, or software component attempts to access data, but that data is not found in its designated, faster cache memory. This necessitates retrieving the data from a slower, higher-latency source, such as main memory, disk storage, or a remote system, incurring a performance penalty.
Key Characteristics
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- Performance Impact: A
cache misssignificantly increases the latency of data access, consuming more CPU cycles and I/O resources, thereby degrading overall system and application performance. - Hierarchy of Caches: Can occur at various levels, including CPU L1/L2/L3 caches, storage controller caches (e.g., for DASD), and software-managed caches like DB2 buffer pools or CICS data tables.
- Causes: Often results from poor data locality, insufficient cache size for the working set, or inefficient data access patterns (e.g., random access over sequential).
- Resolution Mechanism: Upon a miss, the system automatically fetches the required data from the next slower level in the memory or storage hierarchy and places it into the cache, hoping for future hits.
- Monitoring:
Cache missrates andhit ratiosare critical performance metrics monitored using tools like RMF (for CPU/storage), SMF (for system-wide data), DB2 PM, and CICS monitoring tools.
- Performance Impact: A
Use Cases
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- CPU Cache: A COBOL program executing on a z/OS CPU attempts to access a data item (e.g., a variable in working storage), and that item is not present in the CPU's L1, L2, or L3 cache, forcing a retrieval from main memory.
- Storage Controller Cache: A batch job performs an I/O operation to read a record from a VSAM KSDS dataset, but the required data block is not found in the DASD storage controller's cache, leading to a physical disk read.
- DB2 Buffer Pools: A CICS transaction queries a DB2 table, and the specific data page or index page required is not present in the assigned DB2 buffer pool, triggering a synchronous read from the DB2 dataset on disk.
- CICS Data Tables: A CICS application attempts to retrieve an entry from a CICS User-Maintained Data Table (UMT) or a Shared Data Table (SDT), and the entry is not found in the table's memory space, potentially requiring a read from an external file or database.
Related Concepts
A cache miss is the inverse of a cache hit and is fundamental to understanding the performance implications of caching mechanisms across the mainframe ecosystem. It directly impacts system throughput and response time by increasing CPU utilization and I/O latency. Effective management of buffer pools (e.g., DB2, IMS) and data spaces (e.g., CICS data tables) is crucial in minimizing cache misses and leveraging locality of reference for optimal performance.