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Instruction Counter

Program Counter

Enhanced Definition

In IBM mainframe processors, the Instruction Counter, often referred to as the Program Counter (PC) in broader computing contexts, is a special-purpose register within the CPU that holds the memory address of the *next* instruction to be fetched and executed. It is fundamental to controlling the sequential flow of program execution by always pointing to the location of the next operation.

Key Characteristics

- Special-Purpose Register: It is a dedicated hardware register within the CPU, distinct from general-purpose registers (GPRs) used for data manipulation.
- Next Instruction Address: Always points to the starting address of the instruction that the CPU will fetch and execute *after* the current instruction completes.
- Automatic Increment: After an instruction is fetched, the Instruction Counter is automatically incremented by the length of that instruction, preparing for the next sequential instruction fetch.
- Modifiable by Branch Instructions: Its value can be explicitly altered by branch, jump, or call instructions (e.g., BAL, BCR, B in System/390 or z/Architecture assembly), allowing for non-sequential program flow.
- Part of the Program Status Word (PSW): In z/Architecture, the Instruction Counter (or Instruction Address) is a field within the Program Status Word (PSW), which encapsulates the entire state of the CPU. The PSW also contains other critical information like condition code, interrupt masks, and addressing mode.
- Addressing Mode Dependent: Its effective size and interpretation depend on the current addressing mode (24-bit, 31-bit, or 64-bit) specified in the PSW, determining the maximum addressable memory range for instructions.

Use Cases

- Sequential Program Execution: The primary use case is to manage the continuous, sequential execution of instructions within a COBOL program, CICS transaction, or JCL step, by always pointing to the next instruction in memory.
- Branching and Looping: Essential for implementing control flow constructs like IF/THEN/ELSE, DO/WHILE, or GOTO in high-level languages, which translate into branch instructions that modify the Instruction Counter to alter execution path.
- Subroutine Calls and Returns: When a program calls a subroutine, the current Instruction Counter value (the return address) is typically saved (e.g., in a GPR or on the stack) before the PC is loaded with the subroutine's entry point. Upon return, the saved address restores the PC.
- Interrupt and Exception Handling: During an interrupt (e.g., I/O completion, program check), the current Instruction Counter (as part of the PSW) is saved, and a